Over all a nice job, but a few problems. All the parts are pretty much the same so I’ll use the HDC1010 as an example. First I ran the part through FritzingCheckPart.py (available here)
which produces these errors:
Error 69: File
‘svg.breadboard.HDC1010_c392f30c95444e16ff173850711d1017_2_breadboard.svg.bak’
At line 17
Found a drawing element before a layerId (or no layerId)
Error 69: File
‘svg.schematic.HDC1010_c392f30c95444e16ff173850711d1017_2_schematic.svg.bak’
At line 17
Found a drawing element before a layerId (or no layerId)
Error 18: File
‘part.HDC1010_15573dc279dec0c8441631364ba10f98_1.fzp.bak’
Connector connector0terminal is in the fzp file but not the svg file. (typo?)
svg svg.schematic.HDC1010_c392f30c95444e16ff173850711d1017_2_schematic.svg.bak
Error 18: File
‘part.HDC1010_15573dc279dec0c8441631364ba10f98_1.fzp.bak’
Connector connector1terminal is in the fzp file but not the svg file. (typo?)
svg svg.schematic.HDC1010_c392f30c95444e16ff173850711d1017_2_schematic.svg.bak
Error 18: File
‘part.HDC1010_15573dc279dec0c8441631364ba10f98_1.fzp.bak’
Connector connector2terminal is in the fzp file but not the svg file. (typo?)
svg svg.schematic.HDC1010_c392f30c95444e16ff173850711d1017_2_schematic.svg.bak
Error 18: File
‘part.HDC1010_15573dc279dec0c8441631364ba10f98_1.fzp.bak’
Connector connector3terminal is in the fzp file but not the svg file. (typo?)
svg svg.schematic.HDC1010_c392f30c95444e16ff173850711d1017_2_schematic.svg.bak
Error 18: File
‘part.HDC1010_15573dc279dec0c8441631364ba10f98_1.fzp.bak’
Connector connector4terminal is in the fzp file but not the svg file. (typo?)
svg svg.schematic.HDC1010_c392f30c95444e16ff173850711d1017_2_schematic.svg.bak
The layerId is missing in both breadboard and schematic. The effect of that is the part won’t export as an image (svg, png, jpg etc.) the wires to the part will appear but the part itself will be blank. The easiest way to fix that is to rename group Layer_x0020_1 here to breadboard
the layerId needs to match the value in the .fzp file in this case breadboard, found here in file part.HDC1010_15573dc279dec0c8441631364ba10f98_1.fzp
<breadboardView>
<layers image="breadboard/HDC1010_c392f30c95444e16ff173850711d1017_2_breadboard.svg">
<layer layerId="breadboard"/>
</layers>
</breadboardView>
Schematic:
In the schematic case the layerId needs to be schematic. As well, while the current schematic will work, it is preferable to have one that conforms to the graphics standard available here:
https://fritzing.org/fritzings-graphic-standards
It is preferable (so all the parts match in schematic) that parts look like this (this was generated by the Inkscape Fritzing-Schematic extension and meets the graphics standards.)
Here the pin is .110in long and has a .01in by .01in terminalId on the end of the pin. The effect of this in Fritznig is this:
The top is your current part, under it is a par t from core in the standard format. Note the pin is .1in (actually probably 0.105in or 0.11in) long and is colored red by Fritzing. The longer pin makes connections to it easier. The terminalId is on the left end of the pin (and if it is missing, the connection will be to the center of the pin which is incorrect!) Here I intentionally deleted the connector1terminal element to demonstrate what happens when the terminalId is missing.
In Fritzing that produces this:
Here pin1 has a correctly positioned terminalId so the wire terminates as it should at the end of the wire. Pin2 however is missing its terminalId and the wire terminates in the middle of the pin (which is incorrect!) As well it is desirable to set the label value in the fzp file to M (for module) rather than HDC1010 (which as we see in the image above gets truncated to HDC to form label HDC1. So replace
<label>HDC1010</label>
in the fzp file with
<label>M</label>
to make that change. It is also desirable to move the silkscreen group in the pcb svg to be above the two copper groups like this:
to look like this:
FritzingCheckPart produces this warning about the layerIds:
Warning 25: File
‘svg.pcb.HDC1010_c392f30c95444e16ff173850711d1017_2_pcb.svg.bak’
At line 123
Silkscreen layer should be above the copper layers for easier selection
in pcb view
(a warning because it doesn’t stop Fritzing from working, it just makes silkscreen select first over the copper layers which is usually not what you want!)
Peter