Peter one other question regarding the pic24fj128ga204. The version I have is the TQFP which is slightly bigger than the QFN. Is there an easy to change the dimensions to the TQPF 10x10x1.0 mm package?
Thanks
Ian
It is relatively easy to do. You need to edit the pcb svg file
svg.pcb.PIC24FJ128GA204_8903ac93cd3db0fdd1143f9428ed518e_1_pcb.svg with Inkscape or another svg editor and change the pad size and spacing. Easy to do if you are familiar with making parts, less so if you are not. You also need to watch for Inkscape doing things like moving pads via transforms (which Fritzing sometimes doesn’t like) and then edit the fzp file to change the package type, In the end it was easier to do it than try and explain what need doing 
. If you keep a copy of the original part’s fzpz file you can uncompress it and try and make the changes to the svg and fzp to match the one I replaced above (which has the new footprint which still needs to be checked against a real part!) if you like.
Peter
Peter
Thanks. I will give it a try.
Ian
Peter
I was able to change the files you indicated. How do I put them back into a .FZPZ zip file?
Thanks
Ian
Just zip them (I typically use 7zip) and change the trailing .zip to .fzpz and you should be away.
Peter
Peter
I have created the part for PIC241FJ128GA204 TQFP. I have provided this as an attachment in case others may want to use it. I used Inkscape and my first attempt did not work when tried to copy some sections and paste. It appears that you need to edit the actual components or they don’t show up in the final part.
If there is a way around this then let me know as it takes a good amount of time to edit every component of the image.
Thanks
Ian
The part looks not bad, check part is happy enough other than the there is a transform in copper1. It can likely be removed by ungrouping copper1 and regrouping it (the ungroup usually removes translates.) Schematic is strange. It is not loading the correct svg for some reason, and I don’t know where it is getting the one it is loading. Fritzing looks like this:
where the text is in the wrong place and the pins are .2 in wide instead of .1in. The svg looks correct:
there isn’t a conflicting svg in core parts so I don’t know why this is happening, I will have to poke further at it.
Peter
Peter
I actually only changed 2 files
- The pcb svg file. The pcb svg looks ok to me but agree that in inkscape the schematic svg looks ok but in fritzing schematic it does not. I did not change the schematic. Also not sure what you meant by copper1. Anyway I ungrouped the entire image in the pcb svg but have not tested further.
2, I changed the FZP file ie QFN TQFP package in the XML.
I am not all that familiar with editing these file and need some help to clean it up as I am not sure how to proceed in getting an FZPZ file that I can use when requesting board manufacture.
Thanks
Ian
I’ve been distracted trying to reproduce a bug (found 2 more, not related but still not the original one) so I’ll try and figure out why schematic is wrong, it shouldn’t be.
You need the silkscreen and copper1 groups or pcb won’t be correct. A through hole part has copper1 with copper0 as a group under that, for SMD (which this is) only copper1 is needed. Removing copper1 should have removed the translates, now you need to select all the pins and group them and name that group copper1 (and all the black silkscreen lines in a group called silkscreen if you also ungrouped them.)
If you post the .fzz file for the final sketch (which will include your part as it isn’t in core) I’ll check it over. Normally the final step is in pcb view File->Export->for Production->Extended gerber. Which will ask for a directory. When you click OK it writes the gerber files which the board house then accepts to make boards. It is a good idea to use a gerber viewer (I use gerbv from the geda project, but there are lots of them) to read and display the gerber files so you are sure the gerbers reflect the real board (there are a number of gerber related bugs in Fritzing.) Then you zip up all the gerber files and send that zip file to the board house.
edit:
My original part has the same schematic problem (I’m not sure how I missed that when I tested it), but I can’t figure out why or how it is making the changes. I have verified (by changing text) that is loading the supplied schematic svg, but I can’t see anything wrong with the svg and have never seen Fritzing do this before. I’ll keep poking.
Peter
Found the problem. With “editable pin labels” set to true Fritzing substitutes a hard coded svg internally for schematic (presumably so it knows where the pin labels are.) I replaced my original part with one that has the schematic svg modified (and which looks invalid but isn’t as it will be substituted) to match the substitute svg so the labels and outline are in the correct place. Long term, I would like to remove that hard coded svg from the code because as noted it is ugly and violates the rule of least astonishment.
Peter
Peter
I am not sure what this means. I need to know if I can use the PIC24FJ128GA204 (TQFP version) I created, when I submit my board for PCB creation?
Thanks
Ian
Yes the latest version that I replaced has the schematic svg modified (not completely, so it looks a little odd in Inkscape but works fine in Fritzing) to match what the code is substituting, so the part now appears correct in schematic in Fritzing. That only affected schematic, not the footprint. So long as you print out the footprint at 1:1 scale and check it against a real part to make sure it is correct, and verify the gerber output with a gerber viewer, your board should be fine. Feel free to upload your final .fzz file and I can check it over (not having the part I can’t verify the footprint though.)
Peter
Peter
I did check the footprint and it is an exact against the actual chip. However, I started to create a new pcb layout with the chip. and it seems to work ok until I ran the DRC (Design Rule Check) and I am getting all route to and from the chip reported as Overlaps. I tried a different chip from the library and I am getting the same result so it doesn’t appear to be a problem with PIC24FJ128GA204. I did try really thin wires but it still reports Overlay errors. Any idea why I would be getting these?
You need to set the grid size down to be able to position the traces far enough apart to pass drc. I’m using 0.01in (down from the default .1in) here and drc passes. You can also relax the default drc rules a bit for really fine pitch SMD but that shouldn’t be needed here.
I had to tweek the position of a couple of the right side traces a bit to get DRC to pass (if you click on the error in the DRC window it will show the conflict in red to tell you where to move.) If that doesn’t fix it, upload the .fzz file and I will have a look.
Peter
Peter
I reduced trace width to 21mm and relaxed the DRC rules - keepout is now .2140 mm. Do you think these are risky for fabrication? Anyway I have attached the FZZ file. Can you take a look at it and tell me which pins or spacing need to be adjusted?Untitled Sketch 2.fzz New.fzz (60.2 KB)
With the warning I’m not a big board expert (I rarely make boards) here are some suggestions: I’m not real sure why DRC is complaining (I may have screwed something up in the part but I can’t see it.) I did reduce the traces on the ICs to 16mils. If you click on a trace and look in Inspector (bottom right window) you can set the trace size to a variety of standard values. I have done parts with much finer spacing than this for people (one was running close to the 8 thou minimum clearance of the usual board houses but the chip worked fine and the user even managed to hand solder it!) One thing I would probably suggest is dragging schematic out and routing it to make sure the schematic matches what you thing you have routed in pcb (it is awfully easy to make mistakes!) The board house will make what the gerber says. I don’t think there will be any problem with this, as nothing but the IC traces (and not all of them) are tripping DRC and the gerber output looks fine to me ) this is the two copper layers gerber output in gerbv:
There are a couple of things (non critical) on the layout as well. There are a couple or redundant vias (circled in red here), in general less vias is better (one less chance of a plating through failure causing problems.) The one on the bottom via on the bottom left can be removed by selecting the bottom trace and clicking move to bottom layer (as the bottom most part is through hole.) Pcb best practice is considered all traces horizontal or vertical, with bends at 45 degrees and straight in to connectors (with a bend a bit out from the connector if required.) but this actually only matters at RF type frequencies and isn’t likely to be an issue here I don’t think. The blue wire on this image will eliminate one of the vias by routing the blue trace on the bottom layer to the pin on the header to a via on the blue wire by the IC (changing two vias in to one)
And here is a copy of your sketch with the IC traces reduced to 16 thou:
Untitled Sketch 2.fzz New-thin-traces.fzz (60.0 KB)
Peter
Peter
Thank you for the assistance - your comments are very helpful. Only Question -
Not sure what you mean by “One thing I would probably suggest is dragging schematic out and routing it to make sure the schematic matches what you thing you have routed in pcb”. Can you clarify?
A picture (or pictures) is worth a thousand words … Schematic view in the sketch currently looks like this:
Many of the parts are currently on top of one another (a Fritzing quirk) so I clicked View->Ratsnest layer (which removes the ratsnest lines so they don’t select and form wires when you move parts), then dragged the components out to make this (where everything should be visible):
(rats nest is visible again to show connections though)
now you want to move things around to a sensible order to be able to route the schematic, and then select a rats nest line and double click on it to create the wire, them move the wire (just like a pcb trace) to route it sensibly:
Here I have done one of the LEDs (and not moved anything to a sensible position, not knowing what that is.) If you do this and only click on rats nest lines (it will let you make new connections that you don’t want quite easily and will reflect those changes as rats nest lines in to pcb!), then the schematic will match what was routed in pcb. If schematic matches what you think you routed all is well, but if there are mistakes they should show up as either missing , extra or mis wired connections in schematic where they should be easier to see than in pcb.
Peter
I did a bit of playing with this. Swapping a few traces between top and bottom layers, and minor route changes got rid of several more vias. Without repositioning any of the parts.
Moving parts around a bit could clean the routing up more, but I know nothing of the physical constraints you are working with for the headers and LEDs.
I ended up deleting a bunch of redundant bend points as well.
Untitled Sketch 2.fzz New-thin-traces.fzz (57.1 KB)