IC Component CReation

Found the problem. With “editable pin labels” set to true Fritzing substitutes a hard coded svg internally for schematic (presumably so it knows where the pin labels are.) I replaced my original part with one that has the schematic svg modified (and which looks invalid but isn’t as it will be substituted) to match the substitute svg so the labels and outline are in the correct place. Long term, I would like to remove that hard coded svg from the code because as noted it is ugly and violates the rule of least astonishment.

Peter

Peter

I am not sure what this means. I need to know if I can use the PIC24FJ128GA204 (TQFP version) I created, when I submit my board for PCB creation?

Thanks

Ian

Yes the latest version that I replaced has the schematic svg modified (not completely, so it looks a little odd in Inkscape but works fine in Fritzing) to match what the code is substituting, so the part now appears correct in schematic in Fritzing. That only affected schematic, not the footprint. So long as you print out the footprint at 1:1 scale and check it against a real part to make sure it is correct, and verify the gerber output with a gerber viewer, your board should be fine. Feel free to upload your final .fzz file and I can check it over (not having the part I can’t verify the footprint though.)

Peter

Peter

I did check the footprint and it is an exact against the actual chip. However, I started to create a new pcb layout with the chip. and it seems to work ok until I ran the DRC (Design Rule Check) and I am getting all route to and from the chip reported as Overlaps. I tried a different chip from the library and I am getting the same result so it doesn’t appear to be a problem with PIC24FJ128GA204. I did try really thin wires but it still reports Overlay errors. Any idea why I would be getting these?

You need to set the grid size down to be able to position the traces far enough apart to pass drc. I’m using 0.01in (down from the default .1in) here and drc passes. You can also relax the default drc rules a bit for really fine pitch SMD but that shouldn’t be needed here.

I had to tweek the position of a couple of the right side traces a bit to get DRC to pass (if you click on the error in the DRC window it will show the conflict in red to tell you where to move.) If that doesn’t fix it, upload the .fzz file and I will have a look.

Peter