The problem is the core part lacks layerIds in breadboard and schematic. AFAIK the only thing that affects is svg export. As well it lacks terminalIds in schematic which causes this in schematic (the top one is the corrected part below):
the solution is to use this part (which is a new part and will load beside the core part) which has both of the above fixes in it. If you click on the current part in your sketch and select delete minus, Fritzing will delete the current part but leave the wires / traces. You then position the new part and drag each trace to make the connection again.
DS2Y-5-DC5V-fixed.fzpz (12.7 KB)
and the test sketch the above image came from:
test-Sketch.fzz (21.3 KB)
The long term solution (after I finish the update to FritzingCheckPart.py) is to clean up core and correct all the broken parts, help with that will be welcome as it is likely to be a big job