About transceiver

The role of 74HC245, why use it, and what effect does it have? What is the working process of it?

Which terms from the article were unclear? It contains the details about requirements, as well as example use case.

The internal ‘working process’ is the functional block diagram in the data sheet.

I believe this part is incorrect for the 245s. The 74ahc240-244 octal buffers have no substrate diodes (and are thus 5V tolerant and will level translate from 5V to 3.3V) the 74ahc245s have substrate diodes and thus are not 5V tolerant (they will clamp the input voltage to a diode drop above 3.3V and thus draw excessive current with a 5V input!)


If so, that original referenced article is totally bogus. The specific example used there is 3 to 5 volt, bidirectional, level shifting

It does look bogus . The 5V supply voltage on their “level translation” example will supply 5V to the 3.3V input of the following chip. If the following chip has substrate diodes the clamp to about 4V will cause excessive current to flow in the substrate diode and possibly damage the 3.3V chip (it will of course appear to work for at least a while!) AFAIK only the ahc and the listed other families (not hc, I tried and blew up a 74hc125 trying to level translate to 3.3V once before discovering the family limitation!) have 5V tolerant inputs and need to be powered at 3.3V to accept a 5V input and produce a 3.3V output from the 5V input without damaging either chip. This is detailed on page 18 of this TI white paper:

The maximum input voltage specified in this 245 data sheet (referenced in the article above) is VCC so in the suggested configuration the 245 will be fine (VCC is 5V on the 245) but the output to the 3.3V logic will also be 5V which is not fine and not level translation unless the 3.3V inputs are 5V tolerant which is not common and thus the advise appears to be incorrect.