Hi guys, thank you very much for everyone’s help. I only just had time to carefully read through all your messages and try what you suggested. It worked after launching Fritzing in debug mode and connecting the oscilloscope in parallel with the multimeter.
It’s a pity that the simulation only runs for a few seconds, but I’m glad it worked in an offline simulator.
To increase the situation time, just increase the horizontal time of the oscilloscope. Time/division
1 Like
@leandroding You need to change the trans simulator duration in the preferences (under beta I think). I put mine to 10 seconds
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@vanepp , does it work after a reinstall?
The simulator tries to load the codemodel from a specific location. In my case from: C:/Users/***/AppData/Local/Programs/Fritzing/lib/ngspice/analog.cm
If you enable the debug window in Fritzing the simulator should say if it manages to load the codemodel file.
If it finds the file should say: Loading codemodel analog.cm from: C:/Users/***/AppData/Local/Programs/Fritzing/lib/ngspice/analog.cm
If not should say: Warning: analog.cm not found at PATH;
Could you check your output and if the it does not find the file, check that if the file exists in that folder.
Nope a reload didn’t fix it.
The simulator gave an error when loading the netlist. Probably some SPICE field is wrong, please, check them.
If the parts are from the simulation bin, report the bug in GitHub.
Errors:
stdout Note: No compatibility mode selected!
stdout Circuit: simulator netlist
stderr Warning: Model issue on line 9 :
stderr .model labpowersuppymodel ilimit(r_out_source=1 r_out_sink=1 i_limit_sou …
stderr Unknown model type ilimit - ignored
stderr Error on line 12 or its substitute:
stderr av1 1_v1_aux 1_v1_aux2 0 1 labpowersuppymodel
stderr MIF-ERROR - unable to find definition of model labpowersuppymodel
Netlist:
Simulator Netlist
- Multimeter, com probe connected to 0 and voltage probe connected to 2
R1 4 3 68k
C1 3 0 47n IC=0
C4 5 0 10p IC=0
D4 6 2 DI_1N4001
D3 1 6 DI_1N4001
XU1 3 4 1 5 3 8 1 0 UA555
.model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 1 labPowerSuppyModel
C3 0 2 10u IC=0
C2 4 6 10u IC=0
*SRC=1N4001;DI_1N4001;Diodes;Si; 50.0V 1.00A 3.00us Diodes, Inc. diode
.MODEL DI_1N4001 D ( IS=76.9p RS=42.0m BV=50.0 IBV=5.00u CJO=39.8p M=0.333 N=1.45 TT=4.32u )
.SUBCKT UA555 32 30 19 23 33 1 21 999
* TR O R F TH D V GND
*
* Taken from ngspice examples: ngspice/examples/p-to-n-examples/555-timer-2.cir at master · imr/ngspice · GitHub and modified to include the ground. And this model has been…
* Taken from the Fairchild data book (1982) page 9-3
*SYM=UA555
*DWG=C:\SPICE\555\UA555.DWG
Q4 25 2 3 QP
Q5 999 6 3 QP
Q6 6 6 8 QP
R1 9 21 4.7K
R2 3 21 830
R3 8 21 4.7K
Q7 2 33 5 QN
Q8 2 5 17 QN
Q9 6 4 17 QN
Q10 6 23 4 QN
Q11 12 20 10 QP
R4 10 21 1K
Q12 22 11 12 QP
Q13 14 13 12 QP
Q14 999 32 11 QP
Q15 14 18 13 QP
R5 14 999 100K
R6 22 999 100K
R7 17 999 10K
Q16 1 15 999 QN
Q17 15 19 31 QP
R8 18 23 5K
R9 18 999 5K
R10 21 23 5K
Q18 27 20 21 QP
Q19 20 20 21 QP
R11 20 31 5K
D1 31 24 DA
Q20 24 25 999 QN
Q21 25 22 999 QN
Q22 27 24 999 QN
R12 25 27 4.7K
R13 21 29 6.8K
Q23 21 29 28 QN
Q24 29 27 16 QN
Q25 30 26 999 QN
Q26 21 28 30 QN
D2 30 29 DA
R14 16 15 100
R15 16 26 220
R16 16 999 4.7K
R17 28 30 3.9K
Q3 2 2 9 QP
.MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
.MODEL QP PNP (BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2 CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
.MODEL QN NPN (IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2 BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5 CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
.ENDS
.option savecurrents
.option interp
.OP
*.TRAN 1ms 100ms
- .AC DEC 100 100 1MEG
.END
The debug log has this to say:
Netlist exporter: ground found
spice * Multimeter, com probe connected to 0 and voltage probe connected to {net connector1}
spice * Multimeter, com probe connected to 0 and voltage probe connected to 2
spice R1 {net connector0} {net connector1} {resistance}
spice R1 4 {net connector1} {resistance}
spice R1 4 3 {resistance}
spice R1 4 3 68k
spice C1 {net connector0} {net connector1} {capacitance} IC=0
spice C1 3 {net connector1} {capacitance} IC=0
spice C1 3 0 {capacitance} IC=0
spice C1 3 0 47n IC=0
spice C4 {net connector0} {net connector1} {capacitance} IC=0
spice C4 5 {net connector1} {capacitance} IC=0
spice C4 5 0 {capacitance} IC=0
spice C4 5 0 10p IC=0
spice D4 {net connector1} {net connector0} DI_1N4001
spice D4 6 {net connector0} DI_1N4001
spice D4 6 2 DI_1N4001
spice D3 {net connector1} {net connector0} DI_1N4001
spice D3 1 {net connector0} DI_1N4001
spice D3 1 6 DI_1N4001
spice XU1 {net connector1} {net connector2} {net connector3} {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 {net connector2} {net connector3} {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 {net connector3} {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 3 {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 3 8 {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 3 8 1 {net connector0} UA555
spice XU1 3 4 1 5 3 8 1 0 UA555
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink={internal resistance} i_limit_source={max current} i_limit_sink={max current})
V{instanceTitle}Aux {net connector0}_{instanceTitle}aux2 {net connector0}{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source={max current} i_limit_sink={max current})
V{instanceTitle}Aux {net connector0}_{instanceTitle}aux2 {net connector0}{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink={max current})
V{instanceTitle}Aux {net connector0}_{instanceTitle}aux2 {net connector0}{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V{instanceTitle}Aux {net connector0}_{instanceTitle}aux2 {net connector0}{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux {net connector0}_{instanceTitle}aux2 {net connector0}{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_{instanceTitle}aux2 {net connector0}{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 {net connector0}_{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_{instanceTitle}aux 5
V{instanceTitle} {net connector0}{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 {net connector0}_{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_{instanceTitle}aux {net connector1} {voltage}
A{instanceTitle} {net connector0}{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
A{instanceTitle} {net connector0}_{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 {net connector0}_{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_{instanceTitle}aux {net connector0}{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 1 labPowerSuppyModel
spice C3 {net connector0} {net connector1} {capacitance} IC=0
spice C3 0 {net connector1} {capacitance} IC=0
spice C3 0 2 {capacitance} IC=0
spice C3 0 2 10u IC=0
spice C2 {net connector0} {net connector1} {capacitance} IC=0
spice C2 4 {net connector1} {capacitance} IC=0
spice C2 4 6 {capacitance} IC=0
spice C2 4 6 10u IC=0
timeStepModeStr: false, numStepsStr: 400, timeStepStr: 1us, animationTimeStr: 5s
Netlist: Simulator Netlist
- Multimeter, com probe connected to 0 and voltage probe connected to 2
R1 4 3 68k
C1 3 0 47n IC=0
C4 5 0 10p IC=0
D4 6 2 DI_1N4001
D3 1 6 DI_1N4001
XU1 3 4 1 5 3 8 1 0 UA555
.model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 1 labPowerSuppyModel
C3 0 2 10u IC=0
C2 4 6 10u IC=0
*SRC=1N4001;DI_1N4001;Diodes;Si; 50.0V 1.00A 3.00us Diodes, Inc. diode
.MODEL DI_1N4001 D ( IS=76.9p RS=42.0m BV=50.0 IBV=5.00u CJO=39.8p M=0.333 N=1.45 TT=4.32u )
.SUBCKT UA555 32 30 19 23 33 1 21 999
* TR O R F TH D V GND
*
* Taken from ngspice examples: ngspice/examples/p-to-n-examples/555-timer-2.cir at master · imr/ngspice · GitHub and modified to include the ground. And this model has been…
* Taken from the Fairchild data book (1982) page 9-3
*SYM=UA555
*DWG=C:\SPICE\555\UA555.DWG
Q4 25 2 3 QP
Q5 999 6 3 QP
Q6 6 6 8 QP
R1 9 21 4.7K
R2 3 21 830
R3 8 21 4.7K
Q7 2 33 5 QN
Q8 2 5 17 QN
Q9 6 4 17 QN
Q10 6 23 4 QN
Q11 12 20 10 QP
R4 10 21 1K
Q12 22 11 12 QP
Q13 14 13 12 QP
Q14 999 32 11 QP
Q15 14 18 13 QP
R5 14 999 100K
R6 22 999 100K
R7 17 999 10K
Q16 1 15 999 QN
Q17 15 19 31 QP
R8 18 23 5K
R9 18 999 5K
R10 21 23 5K
Q18 27 20 21 QP
Q19 20 20 21 QP
R11 20 31 5K
D1 31 24 DA
Q20 24 25 999 QN
Q21 25 22 999 QN
Q22 27 24 999 QN
R12 25 27 4.7K
R13 21 29 6.8K
Q23 21 29 28 QN
Q24 29 27 16 QN
Q25 30 26 999 QN
Q26 21 28 30 QN
D2 30 29 DA
R14 16 15 100
R15 16 26 220
R16 16 999 4.7K
R17 28 30 3.9K
Q3 2 2 9 QP
.MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
.MODEL QP PNP (BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2 CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
.MODEL QN NPN (IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2 BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5 CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
.ENDS
.option savecurrents
.option interp
.OP
*.TRAN 1ms 100ms
- .AC DEC 100 100 1MEG
.END
Running command(remcirc):
Running m_simulator->command(‘reset’):
Running LoadNetlist:
press Ctrl for object (‘QTextEdit’,‘’) focus '(QTextEdit)
I also re downloaded the .fzz file to make sure it is OK and not corrupted locally, but the new download acts the same. I have no clue what is going wrong, it may be something on my system since it only seems to happen to me.
Peter
Hi @fai
Is the file analog.cm or abalog.cm?
I’m on windows 11, Fritzing 1.0.5. I have analog.cm pre installed already.
It is either an error in the spice model, a code problem or a binary package issue
Hi @vanepp
Can you format your above above SPICE Netlist as code block (preformatted text)
Sure, here it is:
Searching for ngspice in the following directories:
C:/Program Files/Fritzing/lib
C:/Program Files/Fritzing
Loading codemodel analog.cm from: C:/Program Files/Fritzing/lib/ngspice/analog.cm
Netlist exporter: ground found
_______________
_______________
_______________
_______________
_______________
_______________
_______________
spice * Multimeter, com probe connected to 0 and voltage probe connected to {net connector1}
spice * Multimeter, com probe connected to 0 and voltage probe connected to 2
spice D3 {net connector1} {net connector0} DI_1N4001
spice D3 1 {net connector0} DI_1N4001
spice D3 1 6 DI_1N4001
spice R1 {net connector0} {net connector1} {resistance}
spice R1 4 {net connector1} {resistance}
spice R1 4 3 {resistance}
spice R1 4 3 68k
spice C2 {net connector0} {net connector1} {capacitance} IC=0
spice C2 4 {net connector1} {capacitance} IC=0
spice C2 4 6 {capacitance} IC=0
spice C2 4 6 10u IC=0
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink={internal resistance} i_limit_source={max current} i_limit_sink={max current})
V{instanceTitle}Aux {net connector0}_{instanceTitle}_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source={max current} i_limit_sink={max current})
V{instanceTitle}Aux {net connector0}_{instanceTitle}_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink={max current})
V{instanceTitle}Aux {net connector0}_{instanceTitle}_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V{instanceTitle}Aux {net connector0}_{instanceTitle}_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux {net connector0}_{instanceTitle}_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_{instanceTitle}_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 {net connector0}_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_{instanceTitle}_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 {net connector0}_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_{instanceTitle}_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux {net connector1} {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 {voltage}
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
A{instanceTitle} {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 {net connector0}_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_{instanceTitle}_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux {net connector0}_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_{instanceTitle}_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 {net connector1} {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 {net connector0} labPowerSuppyModel
spice .model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 1 labPowerSuppyModel
spice XU1 {net connector1} {net connector2} {net connector3} {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 {net connector2} {net connector3} {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 {net connector3} {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 {net connector4} {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 {net connector5} {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 3 {net connector6} {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 3 8 {net connector7} {net connector0} UA555
spice XU1 3 4 1 5 3 8 1 {net connector0} UA555
spice XU1 3 4 1 5 3 8 1 0 UA555
spice C3 {net connector0} {net connector1} {capacitance} IC=0
spice C3 0 {net connector1} {capacitance} IC=0
spice C3 0 2 {capacitance} IC=0
spice C3 0 2 10u IC=0
spice C1 {net connector0} {net connector1} {capacitance} IC=0
spice C1 3 {net connector1} {capacitance} IC=0
spice C1 3 0 {capacitance} IC=0
spice C1 3 0 47n IC=0
spice C4 {net connector0} {net connector1} {capacitance} IC=0
spice C4 5 {net connector1} {capacitance} IC=0
spice C4 5 0 {capacitance} IC=0
spice C4 5 0 10p IC=0
spice D4 {net connector1} {net connector0} DI_1N4001
spice D4 6 {net connector0} DI_1N4001
spice D4 6 2 DI_1N4001
timeStepModeStr: false, numStepsStr: 400, timeStepStr: 1us, animationTimeStr: 5s
Netlist: Simulator Netlist
* Multimeter, com probe connected to 0 and voltage probe connected to 2
D3 1 6 DI_1N4001
R1 4 3 68k
C2 4 6 10u IC=0
.model labPowerSuppyModel ilimit(r_out_source=1 r_out_sink=1 i_limit_source=5 i_limit_sink=5)
V1Aux 1_V1_aux2 1_V1_aux 5
V1 1_V1_aux 0 12
AV1 1_V1_aux 1_V1_aux2 0 1 labPowerSuppyModel
XU1 3 4 1 5 3 8 1 0 UA555
C3 0 2 10u IC=0
C1 3 0 47n IC=0
C4 5 0 10p IC=0
D4 6 2 DI_1N4001
*SRC=1N4001;DI_1N4001;Diodes;Si; 50.0V 1.00A 3.00us Diodes, Inc. diode
.MODEL DI_1N4001 D ( IS=76.9p RS=42.0m BV=50.0 IBV=5.00u CJO=39.8p M=0.333 N=1.45 TT=4.32u )
.SUBCKT UA555 32 30 19 23 33 1 21 999
* TR O R F TH D V GND
*
* Taken from ngspice examples: https://github.com/imr/ngspice/blob/master/examples/p-to-n-examples/555-timer-2.cir and modified to include the ground. And this model has been...
* Taken from the Fairchild data book (1982) page 9-3
*SYM=UA555
*DWG=C:\SPICE\555\UA555.DWG
Q4 25 2 3 QP
Q5 999 6 3 QP
Q6 6 6 8 QP
R1 9 21 4.7K
R2 3 21 830
R3 8 21 4.7K
Q7 2 33 5 QN
Q8 2 5 17 QN
Q9 6 4 17 QN
Q10 6 23 4 QN
Q11 12 20 10 QP
R4 10 21 1K
Q12 22 11 12 QP
Q13 14 13 12 QP
Q14 999 32 11 QP
Q15 14 18 13 QP
R5 14 999 100K
R6 22 999 100K
R7 17 999 10K
Q16 1 15 999 QN
Q17 15 19 31 QP
R8 18 23 5K
R9 18 999 5K
R10 21 23 5K
Q18 27 20 21 QP
Q19 20 20 21 QP
R11 20 31 5K
D1 31 24 DA
Q20 24 25 999 QN
Q21 25 22 999 QN
Q22 27 24 999 QN
R12 25 27 4.7K
R13 21 29 6.8K
Q23 21 29 28 QN
Q24 29 27 16 QN
Q25 30 26 999 QN
Q26 21 28 30 QN
D2 30 29 DA
R14 16 15 100
R15 16 26 220
R16 16 999 4.7K
R17 28 30 3.9K
Q3 2 2 9 QP
.MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
.MODEL QP PNP (BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2 CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
.MODEL QN NPN (IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2 BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5 CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
.ENDS
.option savecurrents
.option interp
.OP
*.TRAN 1ms 100ms
* .AC DEC 100 100 1MEG
.END
Running command(remcirc):
Running m_simulator->command('reset'):
-----------------------------------
Running LoadNetlist:
press Ctrl for object ('QTextEdit','') focus '(QTextEdit)'
press Ctrl+ for object ('QTextEdit','') focus '(QTextEdit)'
press Ctrl+ for object ('QTextEdit','') focus '(QTextEdit)'
press Ctrl+ for object ('QTextEdit','') focus '(QTextEdit)'
press Ctrl+ for object ('QTextEdit','') focus '(QTextEdit)'
press Ctrl+ for object ('QTextEdit','') focus '(QTextEdit)'
press Ctrl+ for object ('QTextEdit','') focus '(QTextEdit)'
Peter
It seems that it found the file (analog.cm) that defines the model (ilimit) and tries to load it, but it seems it fails to load it. I am not sure if it cannot load it because of permissions as it seems your installation is in C/: Program Files/ Or maybe an antivirus, but it seems strange.
Could you check that the file is there? Or disable any antivirus, if you have any. And if you have time, maybe check if installing Fritzing in an user directory fixes it.
Yep it is there and appears readable (if not writable, but I think that is normal)
It looks to be a binary file but is readable
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I can try and change directories on the installer, but the install is the standard default in to program files and has always worked fine for me before.
edit:
I uninstalled Fritzing and reinstalled using c:\Fritizng-test rather than program files and now the simulation works without problem. It appears to be something to do with the default installation, although why only for me I don’t know.
Peter
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For what its worth, I just tested this on a clean Windows 10 VM with Fritzing 1.0.5 (and included the this sketch in our list for release tests)
Fritzing is installed to the Program Files (default) , and the analog.cm file is located like Peter has posted.
The example is already included, but not yet in the simulation examples:
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If you hit the simulate button do you get the same error message I got or does it run clean? It still may be something odd about my system, but it does seem to be related to the code being in program files, as for me it gets the error message if the code is in program files but doesn’t if the code is loaded in a fritzing-test directory on the c: drive rather than program files (indicating something is changing in the permissions on the default load to program files I expect.)
Peter
[image] RAPTOR7762 Regular
July 26This might be a misunderstanding/typo. I asked Google and ChatGPT (my 2 good friends…) and there seems to be analog.cm and abalog.cm, of which analog.cm is preloaded while the lattar (abalog.cm) is not. @fai can you attach abalog.cm?
The file is “analog.cm”. We are using ngspice to solve the circuits. Fritzing makes a netlist of the circuit which specifies the connections between the devices and the mode for each device (which are contained in the part files *.fpz). That netlist is loaded into ngspice to solve the circuit and the results displayed in Fritzing.
See some tutorials here and the ngspice manual:
The power supply uses a codemodel (a model that uses code to define the behaviour of the component rather than equations) as a model for the circuit (to clamp the max current). These codemodels need to be loaded in ngspice and Fritzing does that. The error shows that ngspice does not recognize the model as something failed while loading the library with codemodels. We do not know why, but I guess it was a local issue of Peter´s computer (as it works on a fresh installation and it also worked in Peter´s computer in another installation).
I think this is probably something I did. I remember (but can’t find any documentation on it) changing the permissions on the Program files Fritzing installation directory some time in the past (maybe around the time of the time of Fritzing 0.9.10) due to an installation issue. The uninstall as far as I can see (I just did an uninstall) appears to delete the program files Fritzing directory which should clear any permissions alterations, but may not, it is Windows so who knows what the registry retains? 
I remember thinking it was only the Fritzing directory so there shouldn’t be any security implications. The fact that it works when not installed in program files appears to support that the change to program files is persisting somehow and is likely why this is occurring for me. I think we can safely ignore the issue as it only appears to happen to me and is not a general problem.
Peter
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